1. Field of the Invention
The invention relates to instruction decoding, and more particularly to scanning a queue of variable length instructions to identify instruction elements for decoding.
2. Description of Related Art
General purpose processors typically are based on scalar instruction sets. Processor architectures are either RISC (Reduced Instruction Set Computer) -based or CISC (Complex Instruction Set Computer) -based. Each approach has its advantages and disadvantages, as has been widely discussed in the literature.
RISC architectures have been used in superscalar computer designs. The term "superscalar" describes a computer implementation that improves performance by concurrent execution of scalar instructions. Progress in implementing superscalar RISC architectures has been good. Scalar RISC architectures typically are defined with a pipelined implementation in mind, and include many features which facilitate superscalar implementation. These features include a fixed format and fixed length instructions, explicit instruction operands, and a load/store architecture. Superscalar RISC architectures are described in Johnson, Superscalar Microprocessor Design, Prentice Hall, Englewood Cliffs, N.J., 1991, which is incorporated herein by reference in its entirety.
Although interest has been expressed in achieving superscalar CISC architectures, progress has been hindered in part because few CISC architectures were defined with superscalar implementation in mind. CISC architectures were defined at a time when the principal implementation technique was microcode interpretation of the instruction set, with an emphasis on deciding which operations should be combined into instructions rather than designing operations so that they could be overlapped. While enormously versatile, microcode interpretation does not facilitate development of pipelined architectures or superscalar architectures. Difficulties arise from numerous aspects of conventional CISC architectures, including instruction format complexity. An aspect of the instruction format complexity is instruction length variability.
An example of a CISC instruction format is the instruction format of the model 80486 microprocessor and the Pentium.TM. microprocessor, which are available from Intel Corporation of Santa Clara, Calif. In this instruction format, which inherits characteristics from earlier Intel instruction sets and is generally known as the x86 format, an instruction may have an operation code ("opcode") consisting of one or two opcode bytes, a modify register or memory ("mod r/m") byte, a scale-index-base ("sib") byte, displacement bytes, and immediate date bytes. The opcode specifies the operation code, and may also contain a register identifier. The mod r/m byte specifies whether an operand is in a register or in memory. If the operand is in memory, fields in the mod r/m byte specify the addressing mode to be used. Certain encodings of the mod r/m byte indicate that a second byte, the sib byte, follows to fully specify the addressing mode. The sib byte consists of a 2-bit scale field, a 3-bit index field, and a 3-bit base field. These fields are used in complex memory addressing modes to specify how address computation is done. The displacement byte is used in address computation. The immediate data byte is used for an instruction operand. One or more additional bytes, known as prefix bytes, may appear before the opcode byte. The prefix byte changes the interpretation of the instruction, adding additional complexity.
As is apparent from the foregoing discussion, the length of an instruction in the x86 format is widely variable. The minimum instruction consists of a single opcode byte and is 8 bits long. A long instruction that includes a prefix byte may be 104 bits long. Longer instructions containing more than a single prefix byte are possible as well.
The variable instruction length and other complications of the x86 instruction format has resulted in complex and hence relatively slow decoding circuits. While slow decoding circuits may be acceptable in slow microprocessors and in some CISC microprocessors which handle complex instructions, they seriously impact performance in microprocessors having architectures in which each functional element is optimized for speed.